1. Field of the Invention
This invention relates to a method for producing a layout of element portions for a semiconductor integrated circuit, using a computer.
2. Description of the Prior Art
A method for producing a layout of element portions of a semiconductor integrated circuit, using a computer, provides a layout of element portions of a semiconductor integrated circuit by arranging each element portion in accordance with relative position relation to other element portion in a circuit diagram. Such prior method will be described using FIGS. 17 and 18. FIG. 17 shows a schematic circuit diagram of a given circuit. FIG. 18 is a layout of semiconductor element portions provided by this prior art method. As shown in FIGS. 17 and 18, each element portion is arranged in accordance with a position relation to other element portions in the schematic circuit diagram. The corresponding element portions or parts are designated as like references between FIGS. 17 and 18. However, there is a drawback that there is a tendency that a dead space between element portions becomes larger if such prior art method is applied to providing a layout of a bipolar semiconductor integrated circuit. One of reasons is that in the bipolar semiconductor integrated circuit, an isolating diffused layer is necessary between each element portion. Moreover, in the prior method, there is also a drawback that a dead space between element portions becomes larger when a large amount of a capacity or resistance is arranged. This is because the amount of capacitance and resistance are determined by extending a basic pattern of a capacitor or a resistor in one direction.